(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the etching of passivation layers.
(2) Description of prior art
Integrated circuits are manufactured by forming discrete semiconductor devices in the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices, contacting their active elements, and wiring them together to create the desired circuits. The wiring layers are formed by depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into the openings. A conductive layer is applied over the insulating layer which is then patterned and etched to form wiring interconnections between the device contacts, thereby creating a first level of basic circuitry. The circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with via pass throughs.
Depending upon the complexity of the overall integrated circuit, one or two levels of patterned polysilicon conductors and two or more levels of metallurgy generally used to form the necessary interconnections and to direct the wiring to large metal pads to which the chip's external wiring connections are bonded.
The metal wiring layers, typically of an aluminum alloy containing copper and silicon, are deposited by sputtering or vacuum evaporation. The final metallization layer includes bonding pads which are typically located in the periphery of the integrated circuit. After the final metallization layer is patterned a passivation layer is applied. This layer seals the device structures on the wafer from contaminants and moisture, and also serves as a scratch protection layer. The passivation layer typically consists of a layer of silicon nitride or phosphosilicate glass (PSG) deposited over a layer of silicon oxide. These layers are deposited by plasma enhanced chemical vapor deposition (PECVD). Openings to the bonding pads are then patterned with photoresist and etched by a plasma etching process.
Referring to FIG. 1, there is shown a cross section of an integrated circuit chip on wafer 10. A multilevel wiring structure is represented by the layer 12. An aluminum alloy bonding pad 16 resides atop the uppermost inter metal dielectric(ILD) layer 14, in a peripheral region 30 of the integrated circuit chip. Interconnective wiring lands 17,18,19, some of which connect to bonding pads, are located over the device region 40 and form the uppermost wiring level of the integrated circuit. The bonding pad 16 is typically provided with a top anti reflective coating(ARC) of TiN(not shown) which is used during the photolithographic patterning of the metal layer. The passivation layer 20 forms a protective coating over the integrated circuit. After the deposition of the passivation layer 20, a layer of photoresist 24 is applied and patterned to provide an opening 26 to the bonding pad 16 so that the pad may be wire bonded to the external chip package.
In a conventional process the passivation layer 20 is etched by reactive ion etching(RIE) or plasma etching using well known etchants containing fluorocarbons. A problem with the conventional anisotropic RIE process for etching the passivation layer 20 to expose bonding pads is caused by thin regions of photoresist occurring over the edges 28 of metal lines. The thinning of the photoresist is related to the spacing between the lines, not occurring over narrowly spaced lines 17 and 18, but significant over the edges of the wider spaced lines 18 and 19 at over the bonding pad 16 edges.
FIG. 2 shows the photoresist profile after etching the passivation layer to form the bonding pad opening 26 using RIE. Because of the relatively low selectivities of the oxide and nitride layers relative to photoresist, the thin regions 28 are often penetrated by the etchant resulting in damage to the passivation layer. The obvious solution to this problem is to use a thicker photoresist layer. The photoresist thicknesses typically used for this process are of the order of 2.5 microns. In order to avoid penetration at the thin regions over the metal lands by the passivation layer RIE, photoresist coatings of greater than 3.5 microns are required. A thicker photoresist layer slows the photolithography step thereby reducing its throughput. In addition thicker photoresist coatings require a higher exposure energy and tend to under develop. A better solution to the problem is to improve the etch selectivity of the passivation layer etch.
A number of etchant chemistries have been developed and applied in the semiconductor industry, each combination typically finding a niche application to a unique problem. New chemistries have replaced earlier ones with added benefits in unique applications. A few are cited in Chang, C. Y., and Sze, S. M., ULSI Technology, McGraw-Hill, New York (1997), p354. Carmody, et.al., U.S. Pat. No. 5,549,784 cites the addition of helium to the etchant chemistry for the formation of contact openings. The helium addition reduces gate charging resulting from damage to the gate oxide.
Process variations such as replacing single step process operations with multiple step operations have solved numerous processing problems in the past, many of which arose as a direct result of the trend toward increasing device density and integrated circuit miniaturization. Shan, et.al., U.S. Pat. No. 5,296,094 cites a method for contact etching using a two step approach wherein a problem of micro masking is resolved. A first step etches the bulk of the insulator material in the opening under conditions to avoid micro masking and a second step etches the remainder of the insulator material under conditions giving a high etch rate selectivity.
Meyer, U.S. Pat. No. 5,182,234 shows a method for etching silicon isotropically or anisotropically with SF.sub.6 /O.sub.2 mixtures wherein the amount of O.sub.2 in the gas flow determines the degree of isotropy.